the VLSI 2021 Symposia (plural, since there is a semiconductor technology track and a circuits and systems track) will be a virtual event to be held the week of June 12. Normally, VLSI alternates between Hawaii and Japan. The “venue” for this year is Japan.

The theme is “VLSI Systems for Lifestyle Transformation”.

2021 Circuit Symposium President Ken Takeuchi made the comments in his invitation:

“Even when Covid-19 is recovered in the future, our society could face a radical transformation in lifestyle. People can come to work in more isolation and are less likely to travel physically for personal and work issues. Microscopic change in the way of life of individuals as well as macroscopic change in social structure such as business organization, town planning and transport can occur. At Symposium 2021, taking these lifestyle transformations into account, we will discuss how cutting-edge VLSIs can contribute to such lifestyle and health transformations.

The first plenary session of the Technology Symposium directly touches the pandemic with “Pandemic Challenges, Technology Answers” ​​presented by Siyoung Choi, President and CEO of Foundry Business at Samsung. Although it has presented challenges to the industry, the pandemic has provided one of the biggest booms for the semiconductor industry, and Samsung should have an interesting perspective on applying the lessons of last year. to its foundry activity.

Between the nanosheets

With so few players involved in the advanced nodes, one would think that there will be less diversity in the technological vision. As we are currently down to only two manufacturers on the most advanced 5nm production nodes (Samsung and TSMC), there is some truth to this point.

On the flip side, however, the technological shift for the front-end of the manufacturing workflow is happening faster than ever as finFETS prepares to retire. Two technologies are on the horizon as the industry must evolve beyond finFET.

The initial technology beyond the finFET will be the nanosheet transistor. It’s largely part of a concept that can also be described as an all-around door or GAA. Nanowire is another term that readers may be familiar with that is just a slightly different flavor of nanoscale foil.

Nanosheet technology receives a full session (with co-optimization of design technology). in session 15 and the clearly titled Nanosheet and DTCO.

IBM, Nvidia, Qualcomm, and Samsung are all represented on the technology co-optimization side, but the nanosheet articles in this session are all from academia.

Other articles on GAA technology are scattered throughout the conference. A couple deserves special attention.

TSMC’s Jin Cai will present CMOS device technology for the next decade as one of the modules of the first VLSI short course Advanced process and peripheral technology to 2nm-CMOS and emerging memory). Cai intends to discuss current finFET technology and give an overview of the nanosheet device with TSMC’s view. TSMC has withstood the next generation, instead extending finFET for the 3nm node. Judging by a similar presentation from the MEI 2019, the hardware can specifically include 2D material channel devices (more on that later).

The second module of the short course is from IMEC: Nanosheet device architectures to enable CMOS scaling to 3nm and beyond: Nanosheet, Forksheet and CFET. This short course topic will be presented by Naoto Horiguchi, IMEC Logic CMOS Device Technology Program Director.

IMEC fork FET (source: VLSI 2021)

As Samsung prepares to launch its multi-bridge channel FET (MBCFET) later this year, it is to be expected that the focus will be on this technology. (Yes, MBCFET is yet another term, Samsung’s trademark for nanosheet transistors.) Samsung is represented elsewhere in the conference, but does not have an entry for MBCFET.

Its Director of Logical CMOS Development introduced the topic as part of the All-Around Door Roadmap for the short course, and IMEC reports specific advancements in fork-foil transistors in the second of the Technology Papers sessions. . Forksheet FET for advanced CMOS scaling: Forksheet-Nanosheet co-integration and dual-function metal gates working in 17nm NP space examines the integration of N and P channel devices to promote the area scaling benefits of the fork sheet structure.

Once the silicon nanosheet and silicon-germanium variants are exhausted, the industry will shift to a fundamentally new class of channel materials.

2D or not 2D …

2D channel transistors will replace nanosheet devices in the next decade. Some landmark studies of these devices were reviewed recently in EE Times. As a more futuristic approach, this technology is more present at VLSI 2021.

There are five papers on 2D materials accepted at this year’s conference, mostly in the third session on technology – Future logic devices.

IMEC is well represented with two articles covering WS2 technology in the logical device session. The first is a device paper detailing the door scaling for double door WS2 transistors.

IMEC WS2 channel transistor (source: IEEE)

The second IMEC paper approaches the commercial feasibility of the 2D material concept by discussing the yield and process consistency for 300mm wafers. The key point is the potential for integrating these transistors into the backend process of the line process for monolithic 3D chips.

On this note, a research paper from Taiwan (National Yang Ming Chiao Tung University and TSRI) will present the results on monolithic 3D integrations for 2D materials. The summary provides an opportunity to highlight certain acronyms that may appear. Whenever I am tempted to truncate “2D hardware channel transistor” to simply 2D or 2D transistor, I hesitate because it reminds of the pre-endFET days. Maybe I’m easily confused.

The NYCU-TSRI summary offers us 2DM and M3D. These may not be the first appearances of acronyms, but there is undeniable efficiency in “M3D-2D electronics” as the authors describe the future monolithic 3D integration of 2D material channel transistors.

Popular 2DMs for study offer attractive processing temperatures for integration with standard backend metal processing. These acronyms will be good to remember as the industry may adopt these technologies over the next decade.

While the logic session and the highlighted articles are interesting, another 2DM article escaped this session to land on the Highlight or session 2. But this follows the plenary sessions and aims to capture the important documents for the conference.

Intel contributors will present Advancing the integration of 2D single-layer NMOS and PMOS transistors from growth to Van Der Waals interface engineering for ultimate CMOS scaling in the third slot of the session.

Intel presents the latest path search results for 2D material transistors (source: VLSI 2021)

For those interested in the future of CMOS and the device’s multi-generation roadmap, this paper is a must-have. Intel will compare progress on MoS2, WSe2and WS2 as well as material growth, gate oxide engineering and contacts.

The GAA and 2DM articles are certainly forward-looking, but not as futuristic as those in the VLSI 2021 timeline. These transistor technologies are becoming well established on the roadmap.

Come back to where you once belonged

Despite the emphasis on very mature technology, there is one article that caught my eye. With the impressive tool investments required for any semiconductor factory, extracting additional generations of old technology has become a sacred art in the business.

In this vein, Applied Materials and the authors of IBM examine the extensibility of double damascene copper below a metal line pitch of 28 nm. Dan Edelstein is on the list of authors. This name will be familiar to those who are as interested in copper interconnect technology as peripherals.

AMAT / IBM researchers disclose two process streams for 10nm trace width metals. A new spin with selective barrier deposition of tantalum nitride and remelted copper (Cu / R-TaN / SB) is proposed for new generation mobile chips. For high performance computing applications, the research team suggests a cobalt / copper composite.

Applied Materials and IBM double-width 10nm line-width damascene metals (source: VLSI 2021)

The flavors of these materials are currently in production, and their continued evolution and viability will be welcome.

The scarf

Don’t take this limited overview as an indication of the breadth of deep tech topics that will be showcased at VSLI 2021. These were just a few highlights that caught my eye, and these only came from the Tech Symposium. This track also offers memory and ferroelectric transistors and many other interesting items to digest with the time saved on the usual commute time for this conference (at least for Europeans and North Americans).

Many EE Times readers are probably more interested in the Circuit Symposium, but that has to wait another day.



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